Previous Years Questions Papers

 






Comments

Post a Comment

Popular posts from this blog

8237 Direct Memory Access (DMA) Controller

Image
 Basic DMA operation The direct memory access (DMA) I/O technique provides direct access to the memory while the microprocessor is temporarily disabled. A DMA controller temporarily borrows the address bus, data bus, and control bus from the microprocessor and transfers the data bytes directly between an I/O port and a series of memory locations. The DMA transfer is also used to do high-speed memory-to-memory transfers. Two control signals are used to request and acknowledge aDMA transfer in the microprocessor-based system. The HOLD signal is a bus request signal which asks the microprocessor to release control of the buses after the current bus cycle. The HLDA signal is a bus grant signal which indicates that the microprocessor has indeed released control of its buses by placing the buses at their high-impedance states. The HOLD input has a higher priority than the INTR or NMI interrupt inputs. The 8237 DMA controller The 8237 DMA controller supplies the memory and I/O with contro...
Read more

Memory mapped I/O and Isolated I/O

Image
As a CPU needs to communicate with the various memory and input-output devices (I/O) as we know data between the processor and these devices flow with the help of the system bus. There are three ways in which system bus can be allotted to them : Separate set of address, control and data bus to I/O and memory. Have common bus (data and address) for I/O and memory but separate control lines. Have common bus (data, address, and control) for I/O and memory. In first case it is simple because both have different set of address space and instruction but require more buses. Isolated I/O – Then we have Isolated I/O in which we Have common bus(data and address) for I/O and memory but separate read and write control lines for I/O. So when CPU decode instruction then if data is for I/O then it places the address on the address line and set I/O read or write control line on due to which data transfer occurs between CPU and I/O. As the address space of memory and I/O is isolated and the name is so....
Read more

Demultiplexing Address/Data Bus AD7- AD0

Image
Demultiplexing Address/Data Bus AD7- AD0  Pin 30 of 8085 is the ALE pin which stands for ‘Address Latch Enable’. ALE signal is used to demultiplex the lower order address bus (AD0 – AD7). Pins 12 to 19 of 8085 are AD0 – AD7 which is the multiplexed address-data bus. Multiplexing is done to reduce the number of pins of 8085. Lower byte of address (A0 – A7) are available from AD0 – AD7 (pins 12 to 19) during T1 of machine cycle. But the lower byte of address (A0 – A7), along with the upper byte A8 – A15 (pins 21 to 28) must be available during T2 and rest of the machine cycle to access memory location or I/O ports. Now ALE signal goes high at the beginning of T1 of each machine cycle and goes low at the end of T1 and remains low during the rest of the machine cycle. This high to low transition of ALE signal at the end of T1 is used to latch the lower order address byte (A0 – A7) by the latch IC 74LS373, so that the lower byte A0 – A7 is continued to be available till the end of the m...
Read more