Microprocessor & Interfaces

The Intel 8259A Programmable Interrupt Controller handles up to eight vectored priority interrupts for the CPU. It is cascadable for up to 64 vectored priority interrupts without additional circuitry. It is packaged in a 28-pin DIP, uses NMOS technology and requires a single a5V supply. Circuitry is static, requiring no clock input. The 8259A is designed to minimize the software and real time overhead in handling multi-level priority interrupts. It has several modes, permitting optimization for a variety of system requirements. The 8259A is fully upward compatible with the Intel 8259. Software originally written for the 8259 will operate the 8259A in all 8259 equivalent modes (MCS-80/85, Non-Buffered, Edge Triggered Table: Pin Description Symbol Pin No. Type Name and Function V cc 28 I Supply: +5V Supply. GND 14 I Ground CS” 1 I ...

Software Interrupts The software interrupts are program instructions. These instructions are inserted at desired locations in a program.   The 8085 has eight software interrupts from RST 0 to 7. If the external device places an  Opcode for any one of the RST instruction (RST 0 to RST 7), then 8085 pushes the contents of  PC onto the stack. It then branches the program control to the vector address of the corresponding RST instruction. The vector address for these interrupts can be calculated as follows:  Interrupt number x 8 = vector address

 Basic DMA operation The direct memory access (DMA) I/O technique provides direct access to the memory while the microprocessor is temporarily disabled. A DMA controller temporarily borrows the address bus, data bus, and control bus from the microprocessor and transfers the data bytes directly between an I/O port and a series of memory locations. The DMA transfer is also used to do high-speed memory-to-memory transfers. Two control signals are used to request and acknowledge aDMA transfer in the microprocessor-based system. The HOLD signal is a bus request signal which asks the microprocessor to release control of the buses after the current bus cycle. The HLDA signal is a bus grant signal which indicates that the microprocessor has indeed released control of its buses by placing the buses at their high-impedance states. The HOLD input has a higher priority than the INTR or NMI interrupt inputs. The 8237 DMA controller The 8237 DMA controller supplies the memory and I/O with contro...

As a CPU needs to communicate with the various memory and input-output devices (I/O) as we know data between the processor and these devices flow with the help of the system bus. There are three ways in which system bus can be allotted to them : Separate set of address, control and data bus to I/O and memory. Have common bus (data and address) for I/O and memory but separate control lines. Have common bus (data, address, and control) for I/O and memory. In first case it is simple because both have different set of address space and instruction but require more buses. Isolated I/O – Then we have Isolated I/O in which we Have common bus(data and address) for I/O and memory but separate read and write control lines for I/O. So when CPU decode instruction then if data is for I/O then it places the address on the address line and set I/O read or write control line on due to which data transfer occurs between CPU and I/O. As the address space of memory and I/O is isolated and the name is so....